#ifndef __ETH_STM32F4xx_H__
#define __ETH_STM32F4xx_H__

#include "stm32f4xx.h"

/* MAC MII Data Register */
#define MMDR_MD             0x0000FFFF  /* MII 16-bit rw data                */

/* MII Management Time out values */
#define MII_WR_TOUT         0x0005000  /* MII Write timeout count           */
#define MII_RD_TOUT         0x0005000  /* MII Read timeout count            */

/* MAC MII Address Register */
#define MMAR_PA             0x0000F800  /* PHY address mask                  */
#define MMAR_MR             0x000007C0  /* MII register address mask         */
#define MMAR_CR             0x0000001C  /* Clock range                       */
#define MMAR_MW             0x00000002  /* MII write                         */
#define MMAR_MB             0x00000001  /* MII busy                          */


/* KSZ8041NL PHY Registers */
#define PHY_REG_BMCR        0x00        /* Basic Mode Control Register       */
#define PHY_REG_BMSR        0x01        /* Basic Mode Status Register        */
#define PHY_REG_IDR1        0x02        /* PHY Identifier 1                  */
#define PHY_REG_IDR2        0x03        /* PHY Identifier 2                  */
#define PHY_REG_ANAR        0x04        /* Auto-Negotiation Advertisement    */
#define PHY_REG_ANLPAR      0x05        /* Auto-Neg. Link Partner Abitily    */
#define PHY_REG_ANER        0x06        /* Auto-Neg. Expansion Register      */
#define PHY_REG_ANNPTR      0x07        /* Auto-Neg. Next Page TX            */
#define PHY_REG_LPNPAR      0X08        /* Link Partner Next Page Ability    */

#define PHY_REG_RECR        0x15        /* Receive Error Counter             */
#define PHY_REG_ICSR        0x1B        /* Interrupt Control/Status          */
#define PHY_REG_PCTRL1      0x1E        /* PHY Control 1                     */
#define PHY_REG_PCTRL2      0x1F        /* PHY Control 2                     */

#define PHY_FULLD_100M      0x2100      /* Full Duplex 100Mbit               */
#define PHY_HALFD_100M      0x2000      /* Half Duplex 100Mbit               */
#define PHY_FULLD_10M       0x0100      /* Full Duplex 10Mbit                */
#define PHY_HALFD_10M       0x0000      /* Half Duplex 10MBit                */
#define PHY_AUTO_NEG        0x3000      /* Select Auto Negotiation           */

#define KSZ8041NL_DEF_ADR    0x05        /* Default PHY device address        */
#define KSZ8041NL_ID         0x00221513  /* PHY Identifier                    */



extern void ETH_Phy_Init(void);
extern void write_PHY (uint32_t PhyReg, uint16_t Value);  
extern uint16_t read_PHY (uint32_t PhyReg);
extern void eth_delay(uint32_t dl);	 

#endif /* __STM32F4xx_H__ */

/*----------------------------------------------------------------------------
 * end of file
 *---------------------------------------------------------------------------*/

